The present invention relates to electronic circuits and more specifically, to methods and circuitry for preventing undesirable output transients resulting from fluctuations in the internal ground voltage level of said circuits.
Integrated circuits are frequently designed to include a number of outputs which, during operation, will be switched simultaneously. While this type of operation is desirable and necessary in many applications, the switching of multiple outputs causes the injection of significant amounts of current into the internal circuit ground node. In application, this ground node is connected to external ground through standard integrated circuit interconnect and an external package pin which is inherently an inductive element. During dynamic operation, current flows from the internal ground node to external ground through the package pin. The inductive characteristics of this pin cause a corresponding shift in the voltage level on the internal ground node with respect to external voltage levels. As current continues to be injected into the internal ground node, both positive and negative voltage fluctuations will be established as defined by the inductor-voltage equation V=L di/dt. It is obvious that the greater the number of simultaneously switched output transistors, the greater the instantaneous current injection from internal to external ground and the larger the voltage transients on the internal ground node.
A particular problem is created by the voltage transients described above when the integrated circuit is designed with internal transistors having a base referenced to an external voltage and an emitter referenced to internal ground. Such designs are very common in, for example, input buffers to a variety of integrated circuit device types. In these designs, the internal transistor as described may erroneously turn on when a sufficient fluctuation in the internal ground voltage causes the emitter voltage to separate adequately from the voltage on the base (referenced to external ground). Since the transistor affected typically drives additional circuitry in the output path, the untimely switching of this device will propagate through the intermediate circuitry and result in undesirable signal fluctuations at the device output. Such internal voltage transient behavior will further exacerbate circuit performance as designers strive to obtain even faster switching speeds and increased numbers of outputs.
Accordingly, a need has arisen for a circuit design that will eliminate the deleterious effects of voltage transients on internal ground nodes in integrated circuits. In particular, a need has arisen for controlling the effects of internal ground voltage fluctuations in integrated circuits designed with transistors that have one electrode referenced to internal ground and a control electrode referenced to an external source. Such compensation circuitry should be suitable for use with a variety of integrated circuit designs that suffer from the problems described.
Several techniques have been developed to address these problems. One technique is set forth in application Ser. No. 881,146 filed Jul. 2, 1986, assigned to the assignee of the present invention, wherein a circuit referenced through a capacitor to the supply voltage Vcc is incorporated to control the voltage on the base of the device affected by the internal ground transients. Additional techniques have been developed to control the operation of the compensation network described in the above application. See, for example, application Ser. No. 942,554, filed Dec. 16, 1986 and assigned to the assignee of the present invention. Yet another design to control the operation of the network described in the above application includes two transistors which operate to disable said network in response to the voltage level at the current input. A first transistor may, for example, have its collector coupled to the control side of the above capacitor and its emitter coupled to internal ground. A second transistor may then be used to control the drive current to the first transistor by having a collector couple to the base of the first transistor and an emitter coupled to a node responsive to the input signal. This last technique is the subject matter of co-pending application Ser. No. 07/149,776 assigned to Texas Instruments Incorporated.
Other designs have been implemented to provide a current path between the base of an output transistor and ground to thereby discharge capacitive feedback Miller current generated during circuit switching. See for example, U.S. Pat. No. 4,330,723 or U.S. Pat. No. 4,593,210. These designs, however are not directed to ground transient compensation and lack the high temperature compensation features of the present invention.
Accordingly, it would be desirable to design a ground transient compensation circuit that actively couples the control electrode of the affected device to internal ground which provides tracking of voltage fluctuations with minimal response time. Moreover, it would be desirable to design a ground transient compensation circuit that eliminates the need for a capacitive element, making circuit operation more predictable and greatly reducing circuit layout area. Finally, it is desirable to provide a compensation circuit which has improved voltage margins for operation at elevated temperatures.